Machine Cycle
Understand the Fetch-Decode-Execute-Store cycle used by the CPU to process instructions.
Interactive Simulation
Machine Cycle: Fetch, Decode, Execute, Store
Ready to start
Press Next Step to begin the fetch-decode-execute-store cycle.
Active in this step
CPU
Control Unit
Program Counter (PC)
10Current Instruction Register (CIR)
-Arithmetic Logic Unit
Accumulator
0ALU Result: -
Memory Address Register (MAR)
-Memory Data Register (MDR)
-Main Memory
| Address | Data/Instruction |
|---|---|
| 0 | |
| 1 | |
| 2 | |
| 3 | 20 |
| 4 | 30 |
| 5 | |
| 6 | |
| 7 | |
| 8 | |
| 9 | |
| 10 | ADD 2 (Add whatever is in location 2 to the accumulator) |
| 11 | ADD 4 |
| 12 | STA 5 |
| 13 | |
| 14 | |
| 15 |